This application claims priority to Korean Patent Application No. 2004-43670 filed on Jun. 14, 2004 in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to a capacitance multiplier, and in particular to a capacitance multiplier with cascaded current amplifiers for enhanced capacitance gain and low power consumption.
2. Description of the Related Art
A PLL (Phase Locked Loop) is commonly used for communication, multimedia, and other applications. FIG. 1 is a block diagram of a conventional PLL (Phase Locked Loop). Referring to FIG. 1, the PLL includes a PFD (Phase Frequency Detector) 100, a charge pump 200, a loop filter 300, a VCO (voltage controlled oscillator) 400, and a frequency divider 500.
The PFD 100 generates an up signal SUP and/or a down signal SDN based on a phase (and frequency) difference between a reference signal SIN and a feedback signal SFEED. The charge pump 200 outputs an output signal having a level corresponding to a state of the up signal SUP and/or the down signal SDN.
After high frequency components of the output signal of the charge pump 200 are removed by the loop filter 300, the filtered output signal VFILT is sent to the VCO 400. The VCO 400 outputs a high frequency signal SO having a frequency corresponding to a direct current (DC) level of the signal VFILT.
The divider 500 generates a low frequency feedback signal SFEED based on the output signal SO from the VCO 400. The feedback signal SFEED is fed back to the PFD 100. When the PLL is locked, the output signal SO of the VCO 400 is used for synchronizing the phase of signals in various parts of a circuit.
FIG. 2 shows a circuit diagram of the charge pump 200 and the loop filter 300 in the PLL of FIG. 1. Referring to FIG. 2, the charge pump 200 includes an inverter 210 for inverting the up signal SUP, a PMOSFET (P-channel metal oxide semiconductor field effect transistor) MP1 having a source coupled to a high power supply VDD, a gate coupled to an output of the inverter 210, and a drain having the signal VFILT generated thereon. The charge pump 200 also includes an NMOSFET (N-channel metal oxide semiconductor field effect transistor) MN1 having a drain coupled to the drain of the PMOSFET MP1, a gate having the down signal SDN applied thereon, and a source coupled to a low power supply VSS. The low power supply VSS may have a negative voltage or a ground voltage.
The loop filter 300 includes a resistor RLF1 having one end coupled to the drain of the NMOSFET MN1, a first capacitor CLF1 coupled between the other end of the resistor RLF1 and the low power supply VSS, and a second capacitor CLF2 coupled between the drain of the NMOSFET MN1 and the low power supply VSS. When the loop filter 300 is implemented within a semiconductor chip, the first capacitor CLF1 disadvantageously occupies a large area. Thus, it is desired to reduce the size of the first capacitor CLF1.
FIG. 3 shows a circuit diagram illustrating a basic principle of a capacitance multiplier. Referring to FIG. 3, (a) is a circuit diagram of a capacitance multiplier, and (b) is an AC equivalent circuit of the circuit of (a) seen from a node A.
In the circuit of (a), NMOSFETs MN2 and MN3 form a current mirror with a ratio of sizes (Width/Length) of the NMOSFETs MN2 and MN3 being 1:M. A current flowing through the capacitor C1 is substantially the current I flowing through the NMOSFET MN2, and a current flowing through a drain of the NMOSFET MN3 is M times the current I flowing through the NMOSFET MN2.
An input impedance at the node A is represented by the following expression 1:
                    Z        =                                            υ              ⁢                                                          ⁢              in                                      i              ⁢                                                          ⁢              in                                =                      1                          sC1              ⁡                              (                                  1                  +                  M                                )                                                                        〈                  Expression          ⁢                                          ⁢          1                〉            Accordingly, an input capacitance at the node A is (1+M)C1 that is scaled up by a scale factor of M.
FIG. 4 is a circuit diagram of a conventional capacitance multiplier as disclosed in IEEE Journal of Solid-State Circuits, titled “A 2.4 GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase Switching Prescaler and Loop Capacitance Multiplier”. An input admittance of the circuit of FIG. 4 is represented by the following expression 2:
                    Y        =                                            i              ⁢                                                          ⁢              in                                      υ              ⁢                                                          ⁢              in                                =                                    g              OA                        +                          s              ⁡                              (                                  Cp2                  +                                                            (                                              M                        +                        1                                            )                                        ⁢                                                                                  ⁢                    Ci                    ⁢                                                                                  ⁢                                                                  1                        +                                                  s                          ⁢                                                                                                          ⁢                                                      Cp1                                                                                          (                                                                  M                                  +                                  1                                                                )                                                            ⁢                              gm1                                                                                                                                                  1                        +                                                  s                          ⁢                                                                                                          ⁢                                                                                    Ci                              +                              Cp1                                                        gm1                                                                                                                                              )                                                                        〈                  Expression          ⁢                                          ⁢          2                〉            
In the expression 2, Cp1 and Cp2 are the capacitances of parasitic capacitors at the nodes A and B, respectively, and gm1 denotes a transconductance of the NMOSFET MN13. gOA denotes a total conductance at the node A, and M denotes a current gain of a current mirror.
FIGS. 5A and 5B are graphs showing a frequency response of the input impedance of the circuit of FIG. 4. FIG. 5A shows a magnitude of the input impedance of the circuit of FIG. 4, and FIG. 5B shows a phase of the input impedance of the circuit of FIG. 4. Dotted lines in FIGS. 5A and 5B represent graphs illustrating an ideal frequency response.
Referring to FIGS. 5A and 5B, the circuit of FIG. 4 may be used as a capacitance multiplier in the range of a frequency greater than fc1 and a frequency less than fc2. The fc1 and fc2 are represented by the following expression 3:
                                                                        fc1                =                                                      g                    OA                                                        2                    ⁢                                                                                  ⁢                                          π                      ⁡                                              (                                                  M                          +                          1                                                )                                                              ⁢                                                                                  ⁢                    Ci                                                              ,                                                          fc2              =                              gm1                                  2                  ⁢                                                                          ⁢                  π                  ⁢                                                                          ⁢                  Ci                                                                                        〈                  Expression          ⁢                                          ⁢          3                〉            fc1 is designed to be as small as possible for preventing a decrease in the DC gain of the PLL. In particular, gOA is desired to be small.
In order to maintain a phase margin of the PLL, fc2 is desired to be larger than a zero frequency of the loop filter. Therefore, the value of gm1 and thus the level of current flowing through the NMOSFET MN13 are determined depending on an operating frequency of the loop filter.
For obtaining a large capacitance gain in the circuit of FIG. 4 with a large scale factor (M), the NMOSFET MN14 has current that is M times a current flowing through the NMOSFET MN13. Accordingly, the power consumption of the capacitance multiplier of FIG. 4 increases with the scale factor M. Thus, the scale factor (M) is limited to about 20 in an actual application for acceptable power consumption.
Thus, a capacitance multiplier is desired with higher capacitance gain but with low power consumption.